The present application relates to probe-based technologies, and more particularly to a probe head that contains a coining surface and a plurality of probe tips, each of which is integrated on a same side of the probe head.
As is well known in the art, typical semiconductor integrated circuit (IC) chips have layers stacked such that layer features overlay one another to form individual devices and connect devices together. ICs are mass produced by forming an array of chips on a semiconductor wafer. Each array location is known as a die, and each die may harbor a multilayered structure, such as an IC chip or a structure for test or alignment. The surface layer of each chip or die is typically populated by probe-able off-chip pads for connecting to chip power and input/output (I/O) signals.
As transistor technologies have evolved, chip features and devices have become smaller and have minimum dimensions that typically are well below one micrometer (1 μm) or 1 micron. Smaller chip features and devices allow IC manufacturers to integrate more function in the same chip real estate. Packing more function on each die typically means providing more I/O signals and power connections for each die. Each die has at least one surface pad for each I/O signal and a number of power (supply and ground) connection pads. Providing these I/O signals and supply as the die are shrinking in size, therefore, drives more stringent off-chip connection requirements, i.e., increasingly dense pad arrays. On a typical state of the art IC wafer, for example, the surface layer of each die may be populated by several thousand connection pads, arranged in an area array. As the number of connection pads increases for a given die size, the pitch of the pads decreases from a standard of about 200 microns, to below 50 microns.
Further, these very densely packed chip pads may also be populated with solder balls, also known as bumps, which are typically composed of lead-tin (PbSn) solder or lead-free solder. The solder balls are formed or bumped onto the pads forming non-uniform height bump arrays which are difficult to test with existing compliant probes. For example, some probes may fully “bottom out” during the testing of the bump arrays, while other probes may not make sufficient contact with the some of the bumps within the bump array. Variation in the height and mechanical properties of these probes requires them to be very compliant, resulting in structures which can be damaged by physical contact or by passing high electrical current. The manufacturing cost of these probes is high, and repair of these probes is difficult. As the pitch decreases, both the probe manufacturing cost and cost of repair increases rapidly, with no known solutions for area array pitches below 50 microns.
Also, the non-uniform height bump arrays may cause damage to the probe and/or damage to the bumps themselves may occur with existing probe technology. There are two root causes of bump non-uniformity. The deposition rate of the plating process used to deposit the bumps depends on the local density of bumps, resulting in different bump heights near the edges of the die and other locations where there are variations in the bump array density. To some extent, this effect is moderated by the fact that as the pitch decreases, the size of the bumps also decreases, resulting in a relatively smaller plating non-uniformity. A second cause is photolithographic variation in the via size which defines the bump area to be plated. As the pitch decreases, the relative variation in bump size from this mechanism becomes larger.
An important consequence of decreasing pitch and increasing bump count per die is the force required to probe and achieve good electrical contact over the full array. For conventional compliant probe technology, forces in the range of 1 to 3 grams per pin are required. A standard die with 10,000 bumps would thus require 10 to 30 kg of force to probe. As the bump count per die increases to 100,000 bumps, the forces required are large enough to severely impact the chuck and stage movement portions of the probe station, as well as the probe card fixturing.
In view of the above, there is a need for providing a probe that can be used to test the various bumps of each bump array that are present on a surface of a semiconductor wafer that circumvents the problems associated with non-uniform bump arrays.